Coherency management for a “switchless” distributed shared memory computer system
US7111130B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2006 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Apr 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.