Burst mode implementation in a memory device
US7111143B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2003 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Sep 24, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device, such as a DRAM, includes a memory array that is accessible for writing data in and reading data out, and a command decoder that decodes input control signals to produce commands for accessing the memory array. The set of commands for controlling access to the memory device can include a first memory access command for accessing the memory array using a first burst length, a second memory access command for accessing the memory array using a second burst length, and a terminate command that terminates a current memory access. The memory device can include a mode register that stores memory access parameters associated with accessing the memory array, including the burst lengths. Access to the memory array is switchable between the first burst length and the second burst length without altering the memory access parameters in the mode register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.