Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine
US7111146B1 · kind B1 · utility
27Cited by
1References
15Claims
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Key dates
| Filing date | Jun 27, 2003 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Jan 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host machine context and executing a virtual machine application within a virtual machine context. A plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context are stored within a TLB. Memory protection bits for the plurality of TLB entries are logically combined to enforce memory protection on the virtual machine application.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.