Circuit clustering during placement
US7111262B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2003 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Jul 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method (100) of physical circuit design can include the steps of packing components (110) of a circuit design that are dependent upon an architecture of the circuit design and assigning initial locations (115) to each component of the circuit design. The components of the circuit design can be clustered (120) by combining slices and including slices into configurable logic blocks according to design constraints, while leaving enough white space in the configurable logic blocks for post-placement circuit optimizations. The components of the circuit design then can be placed (125) to minimize critical connections. The circuit design can be declustered (130) to perform additional placer optimization tasks (135) on the declustered circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.