Multiple voltage integrated circuit and design method therefor
US7111266B2 · kind B2 · utility
13Cited by
12References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2003 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Dec 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.