Thread signaling in multi-threaded processor
US7111296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2003 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Jul 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.