Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
US7112495B2 · kind B2 · utility
204Cited by
81References
71Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 5, 2003 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Dec 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.