Ternary content addressable memory cell
US7112831B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2004 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Oct 21, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Ternary CAM cells are provided. The ternary CAM cell includes a pair of half cells. Each of the half cells includes an isolation layer formed at a predetermined region of a semiconductor substrate to define a match cell active region. A search gate electrode and a node gate electrode are placed to cross over the match cell active region. A match line is electrically connected to the match cell active region, which is adjacent to the node gate electrode and is located opposite the search gate electrode. An SRAM cell is provided at the semiconductor substrate adjacent to the match cell active region. The node gate electrode is electrically connected to one of a pair of storage nodes of the SRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.