High voltage tolerant I/O circuit using native NMOS transistor for improved performance
US7113018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2004 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Nov 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An I/O circuit between a low voltage circuit and a high voltage circuit includes a switching device, a native device and a gate control logic circuit. The switching device provides an output signal to the high voltage circuit in response to a data input signal received from the low voltage circuit. The native device passes the data input signal to control an on or off state of the switching device. The gate control logic circuit operates in an output disabled mode and an output enabled mode. In the output disabled mode, the gate control logic circuit disables the native device for preventing a leakage current passing therethrough. In the output enabled mode, the gate control logic circuit enables the native device to pass the data input signal through without a substantial voltage drop, thereby enhancing a switching speed of the switching device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.