Memory systems and methods
US7113418B2 · kind B2 · utility
32Cited by
4References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2003 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Jan 24, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Memory systems and methods are described. In one embodiment, a circuit board has front and back surfaces. At least one memory device having a plurality of pins is mounted on the front surface of the circuit board. At least one other memory device having a plurality of pins is mounted on the back surface of the circuit board. The memory devices are mounted on the circuit board such that at least some pins from the one memory device align with at least some pins of the other memory device to provide aligned pin pairs. A via is disposed in the circuit board and extends between and connects individual pins of an aligned pin pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.