Semiconductor integrated circuit device
US7113421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2005 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | May 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.