Non-volatile RAM cell and array using nanotube switch position for information state
US7113426B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2004 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Jul 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Non-Volatile RAM Cell and Array using Nanotube Switch Position for Information State. A non-volatile memory array includes a plurality of memory cells, each cell receiving a bit line, word line, and release line. Each memory cell includes a cell selection transistor with first, second and third nodes. The first and second nodes are in respective electrical communication with the bit line and the word line. Each cell further includes an electromechanically deflectable switch, having a first, second and third node. The first node is in electrical communication with the release line, and a third node is in electrical communication with the third node of the cell selection transistor. The electromechanically deflectable switch includes a nanotube switching element physically positioned between the first and third nodes of the switch and in electrical communication with the second node of the switch. The second node of the switch is in communication with a reference signal. Each nanotube switching element is deflectable into contact with the third node of the switch in response to signals at the first and second node of the cell selection transistor and is releasable from such contact i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.