Clock control circuit for controlling the clock phase of a transceiver
US7113561B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 27, 2003 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Mar 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock phase control circuit is provided for controlling the clock phase of a transceiver, having a sampling circuit for sampling an analog received signal with a sampling clock signal; an echo signal compensation circuit for compensating an echo signal which is produced by means of a transmit signal transmitted by the transceiver, it being possible to set the echo signal compensation circuit in an adaptive fashion as a function of a setting signal; a control circuit for generating a control signal for controlling the clock phase, which control signal specifies the phase deviation between the signal phase of the sampling clock signal and a setpoint signal phase of an ideal sampling clock signal; a loop filter for filtering the control signal; a phase counter for generating the sampling clock signal as a function of the filtered control signal described [sic]. An amplitude limiting circuit which limits the amplitude of the filtered control signal to a limiting value is provided between the loop filter and the phase counter, the limiting value depending on the setting signal for the echo signal compensation circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.