Test circuit provided with built-in self test function
US7114113B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2003 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Nov 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31926
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test circuit includes an input circuit for inputting data to select a test mode relative to a circuit to be tested and outputting result of selection of the test mode in synchronization with a first clock, a pattern generation circuit for responding to result of selection of the test mode, generating a test pattern in synchronization with a second clock and outputting the test pattern to the circuit to be tested and a comparator circuit for inputting result of test of the circuit to be tested in synchronization with the second clock, and comparing coincidence/non-coincidence between the result of the test and the test pattern supplied to the circuit to be tested. The test circuit further includes an output circuit for holding result of comparison by the comparator circuit and outputting the result of comparison in synchronization with the first clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.