Methods of fabricating flash memory cell having split-gate structure using spacer oxidation process
US7115470B2 · kind B2 · utility
4Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | May 7, 2004 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Oct 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a method of fabricating a split-gate flash memory cell using a spacer oxidation process. An oxidation barrier layer is formed on a floating gate layer, and an opening to expose a portion of the floating gate layer is formed in the oxidation barrier layer. Subsequently, a spacer is formed on a sidewall of the opening with a material layer having insulation property by oxidizing, and an inter-gate oxide layer pattern between a floating gate and a control gate is formed in the opening while the spacer is oxidized by performing an oxidation process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.