Sacrificial annealing layer for a semiconductor device and a method of fabrication
US7115479B2 · kind B2 · utility
5Cited by
28References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2002 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Nov 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/268
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Numerous embodiments of a method and apparatus for a sacrificial annealing layer are disclosed. In one embodiment, a method of forming a sacrificial annealing layer for a semiconductor device comprises forming one or more sacrificial layers on at least a portion of the top surface of a semiconductor device, annealing at least a portion of the device, and removing a substantial portion of the one or more sacrificial layers, where the removing results in no substantial physical alterations to the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.