Circuit for generating a centered reference voltage for a 1T/1C ferroelectric memory
US7116572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2004 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Feb 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.