Processor architecture and a method of processing
US7116680B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2001 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | May 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A process and architecture to simplify the implementation of a high-speed scheduler. A traditional packet based scheduler works the length of the packet. Instead, the present invention uses a transmit queue that determines how many times a portion of a packet needs to be transmitted independent of the process to modify or transform the packet. The packet could be an ATM cell, it could be a fabric cell, or it could be a portion of a frame-based transmission of the packet. As a result, the transmit queue need only determine how many times (times to transmit (TTT)) to schedule transmission of part of the packet. The determined TTT from the transit queue takes into account the packet-based modifications that will be performed on the packet. The TTT is used to determine how many cells the packet needs to be divided into. In another illustrative embodiment, the number of cells or the TTT is determined prior to adding or removing data from the packet. In a further illustrative embodiment, the transmit queue is separate from the circuitry that modifies the packet. In other words, determining the TTT for a packet is separate from the process of modifying the packet for transmission.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.