Method and apparatus to facilitate self-testing of a system on chip
US7117416B1 · kind B1 · utility
11Cited by
13References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 23, 2004 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Dec 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318516
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for providing a system-on-a-chip comprising a processor and a configurable system logic (CSL) including a plurality of banks arranged in an array coupled to the processor. The system on a chip further includes a built-in self test (BIST) mechanism coupled to the CSL to perform tests on the CSL to verify that the banks and interconnections between the banks are functioning properly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.