Current scheduling system and method for optimizing multi-threshold CMOS designs
US7117457B2 · kind B2 · utility
10Cited by
4References
54Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2003 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Jul 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention provides a mechanism for minimizing the switching time degradation of MTCMOS circuits while at the same time minimizing the area overhead due to the MTCMOS switch circuitry. This optimization is achieved by scheduling the current flow, due to the switching events of the MTCMOS logic cells, such that only temporally mutually exclusive currents, or currents whose cumulative sum is less than a predetermined value, can flow in any given switch cell. Techniques for current event merging and current event culling, and techniques for handling timing and current variances may be used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.