Generation of design views having consistent input/output pin definitions
US7117471B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2004 |
| Grant date | Oct 3, 2006 |
| Priority date | — |
| Expiry date | Apr 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Generation of consistent connection data for a first circuit embedded in a second circuit. In one approach, a master file is established with design data that includes for each pin in the embedded circuit, a hardware description language (HDL) pin name from an HDL description of the embedded circuit, a schematic pin name of the second circuit to which a corresponding pin in the embedded circuit is to connect, a signal direction associated with the pin, and a name of a clock to trigger a signal on the pin. A plurality of design views are generated from the master file. Each design view has a unique format relative to the other design views and includes for each pin in the embedded circuit design, at least the HDL pin name, the associated schematic pin name, and a signal direction associated with the pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.