Placement of a clock signal supply network during design of integrated circuits

US7117472B2 · kind B2 · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Stefan Auracher · Baierbrunn, DE
• Claus Pribbernow · Birkenfeld, DE
• Andreas Hils · Unterhaching, DE
• Juergen Dirks · Holzkirchen, DE
• Manisha R. Patel · Milpitas, US
• James Imper · Mountain View, US

Key dates

• Filing date: Jul 9, 2004
• Grant date: Oct 3, 2006
• Expiry date: Aug 31, 2024

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2117/04
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method of placing a clock signal supply network in a design representation for an integrated circuit. The design representation may comprise a plurality of clockable circuit cells. The method may comprise identifying a first of the clockable circuit cells in the design representation. The method may further comprise identifying a second of the clockable circuit cells in the design representation. The second clockable circuit cell may have a clock timing dependent relation relative to the first clockable circuit cell. The method may further comprise configuring the clock signal supply network. The clock signal supply network may be configured to supply respective clock signals to the first and said second clockable circuit cells. The clock signal supply network may be configured to route the respective clock signals such that a timing difference between the respective clock signals is protected from process, voltage and temperature (PVT) influences.