Juergen Dirks
23Patents
6h-index
24Co-inventors
65Inventor score
Filing activity: Feb 25, 2002 → Aug 27, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7747975B2 | Timing violation debugging inside place and route tool | Physics | 190 | Active |
| US7325215B2 | Timing violation debugging inside place and route tool | Physics | 14 | Expired |
| US7398489B2 | Advanced standard cell power connection | Electricity | 10 | Expired |
| US7441210B2 | On-the-fly RTL instructor for advanced DFT and design closure | Physics | 10 | Active |
| US7000163B1 | Optimized buffering for JTAG boundary scan nets | Physics | 8 | Expired |
| US7191424B2 | Special tie-high/low cells for single metal layer route changes | Physics | 7 | Expired |
| US8219959B2 | Generating integrated circuit floorplan layouts | Physics | 6 | Active |
| US7546560B2 | Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlist | Physics | 6 | Active |
| US7331028B2 | Engineering change order scenario manager | Physics | 5 | Expired |
| US7546568B2 | Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage | Physics | 5 | Active |
| US7117472B2 | Placement of a clock signal supply network during design of integrated circuits | Physics | 4 | Expired |
| US7334206B2 | Cell builder for different layer stacks | Physics | 4 | Expired |
| US7975197B2 | On-chip scan clock generator for ASIC testing | Physics | 4 | Active |
| US7523426B2 | Intelligent timing analysis and constraint generation GUI | Physics | 4 | Expired |
| US7958473B2 | Method and computer program for configuring an integrated circuit design for static timing analysis | Physics | 3 | Active |
| US8584068B2 | Timing violation debugging inside place and route tool | Physics | 3 | Active |
| US8539407B2 | Intelligent timing analysis and constraint generation GUI | Physics | 3 | Active |
| US8572543B2 | Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage | Physics | 1 | Active |
| US8332801B2 | Special engineering change order cells | Physics | 1 | Active |
| US8564337B2 | Clock tree insertion delay independent interface | Physics | 1 | Active |
| US8161447B2 | Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage | Physics | 1 | Active |
| US8863053B2 | Intelligent timing analysis and constraint generation GUI | Physics | 0 | Active |
| US7634748B2 | Special engineering change order cells | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.