Integrating metal layers with ultra low-K dielectrics
US7119008B2 · kind B2 · utility
2Cited by
7References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 18, 2001 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Apr 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1036
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In forming a layer of a semiconductor wafer, a dielectric layer is deposited on the semiconductor wafer. The dielectric layer includes material having a low dielectric constant. Recessed and non-recessed areas are formed in the dielectric layer. A metal layer is deposited on the dielectric layer to fill the recessed areas and cover the non-recessed areas. The metal layer is then electropolished to remove the metal layer covering the non-recessed areas while maintaining the metal layer in the recessed areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.