Method for improving interlevel dielectric gap filling over semiconductor structures having high aspect ratios
US7119017B2 · kind B2 · utility
1Cited by
11References
28Claims
0Family size
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Key dates
| Filing date | Oct 12, 2004 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Oct 12, 2024 |
Classification
- Technology area (CPC F)Mechanical Engineering; Lighting; Heating
- CPC primaryF28F25/08
- WIPO fieldThermal processes and apparatus
- WIPO sectorMechanical engineering
Abstract
A novel sequence of process steps is provided for forming void-free interlevel dielectric layers between closely spaced gate electrodes. Closely spaced gate electrodes having sidewall spacers are formed on a substrate. After using the sidewall spacers to form self-aligned source/drain contacts and self-aligned silicide contacts, the sidewall spacers are removed. By removing the sidewall spacers, the aspect ratio of the gap between adjacent closely spaced gate electrodes is substantially reduced (from greater than 5 to less than 2), thereby preventing voids during the subsequent deposition of an ILD layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.