Data/clock recovery circuit for recovering data and clock signal with high accuracy
US7120216B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 12, 2002 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Aug 31, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data/clock recovery circuit can recover high-rate data using the data as a clock signal. It includes an edge detector, a clock selection signal generating circuit, a clock selection circuit and a synchronizing circuit. The edge detector generates edge position information using a receiver output as a clock signal. The clock selection signal generating circuit generates a clock selection signal in response to the edge position information using the receiver output as the clock signal. The clock selection circuit selects a recovered clock signal from a clock signal group in response to the clock selection signal. The synchronizing circuit synchronizes the receiver output using the recovered clock signal, and outputs it as a synchronized data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.