Bit exactness support in dual-MAC architecture
US7120661B2 · kind B2 · utility
1Cited by
3References
19Claims
0Family size
Assignee
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Key dates
| Filing date | May 29, 2003 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Mar 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arrangement (200) and method for bit exactness support in dual-MAC architecture by detecting when underflow or overflow conditions will occur, and for operating the dual-MAC arrangement in single-MAC mode for at least one cycle upon such detection.This produces the advantages of providing dual-MAC execution with saturation capabilities, with only a small degradation in performance, while employing detection logic that is very small and simple compared to the logic required for a conventional full saturation dual-MAC architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.