Synchronous DRAM with selectable internal prefetch size
US7120754B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2005 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Nov 8, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous memory device and its method of operation which can be set to operate at a plurality of supported prefetch modes. The prefetch mode may be set by programming a portion of a mode register of the memory device or by setting one or more programmable elements. For read operations, the synchronous memory device internally reads data corresponding to the largest supported prefetch size, and outputs read data corresponding to the current mode. For write operations the synchronous memory accepts write data corresponding to the selected prefetch mode and writes the received data to the array. Data words corresponding to data not received are masked from writing via a write masking circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.