Transfer of cache lines on-chip between processing cores in a multi-core system
US7120755B2 · kind B2 · utility
28Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2002 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Jul 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific embodiments are described, using write buffers, fill buffers, and multiplexers, respectively, to achieve the on-chip transfer of data between dedicated caches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.