Apparatus and method for memory management
US7120773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2003 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Oct 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A TLB provided in a memory management apparatus stores an entry for each logical page, and each entry holds an address of a physical page mapped to a corresponding logical page, an index showing the degradation degree of the physical page, and an index showing the access frequency to the logical page. The memory management apparatus accesses a physical page mapped to a desired logical page according to the data stored in the TLB, periodically exchanges the contents between a first physical page mapped to a specific logical page having a largest access frequency index and a second physical page having a smallest degradation index, and then maps the specific logical page to the second physical page. Through the physical page exchange and corresponding mapping process, accesses to each physical page are distributed, so that degradation in storage function is substantially equalized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.