Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment
US7120784B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2003 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Oct 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better results for branch prediction. The branch prediction logic responds to the occurrence of the monitored condition by logically splitting the BHTs and count cache so that half of the address space is allocated to a first thread and the second half is allocated to the next thread. Prediction-generated addresses that belong to the first thread are then directed to the half of the array that is allocated to that thread and prediction-generated addresses that belong to the second thread are directed to the next half of the array that is allocated to the second thread. In order to split the array, the highest order bit in the array is utilized to uniquely identify addresses of the first and the second threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.