Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias including maintaining a substantially constant operating frequency
US7120804B2 · kind B2 · utility
36Cited by
15References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2002 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | May 25, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach for power reduction of an integrated circuit device. In response to detecting a change in an activity factor associated with an integrated circuit device from a first activity factor to a second activity factor, a supply voltage and a body bias associated with the integrated circuit device are adjusted based on the second activity factor to reduce power consumption. For one aspect, the supply voltage and body bias are adjusted to maintain a substantially constant operating frequency for the integrated circuit device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.