Instruction-initiated power management method for a pipelined data processor
US7120810B2 · kind B2 · utility
7Cited by
104References
82Claims
0Family size
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Key dates
| Filing date | Feb 23, 2004 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Nov 1, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to an instruction executed by the pipeline subcircuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.