Mechanism to enhance observability of integrated circuit failures during burn-in tests
US7120842B2 · kind B2 · utility
2Cited by
3References
15Claims
0Family size
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Key dates
| Filing date | Sep 22, 2003 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Nov 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method enhance observability of IC failures during burn-in tests. Scan automatic test pattern generation and memory built-in self-test patterns are monitored during the burn-in tests to provide a mechanism for observing selective scan chain outputs and memory BIST status outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.