Method of setting process parameter and method of setting process parameter and/or design rule
US7120882B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2005 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Apr 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.