Method for manufacturing trench gate semiconductor device

US7122433B2 · kind B2 · utility

Assignee

• KONINKLIJKE PHILIPS ELECTRONICS NV · NL

Inventors

• Steven Peake · Warrington, GB
• Georgios Petkos · Stockport, GB
• Philip Rutter · Stockport, GB
• Raymond J. Grover · Manchester, GB

Key dates

• Filing date: Apr 9, 2004
• Grant date: Oct 17, 2006
• Expiry date: Jul 3, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/519

Abstract

A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e). The lateral extent of the conductive layer (11c) terminates in an edge (11a,11b) that is defined on the trench-etch mask (51).