Two step semiconductor manufacturing process for copper interconnects
US7122466B2 · kind B2 · utility
2Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2003 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Jul 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention is a method of manufacturing copper interconnects 30 on a semiconductor wafer 10 where an electroplating process is used to deposit a first layer of copper grains 30d having an initial grain size and a second layer of copper grains 30e having a different initial grain size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.