SOI wafer and process for producing it

US7122865B2 · kind B2 · utility

Assignee

• Siltronic AG · DE

Inventors

• Robert A. Holzl · Tustin, US
• Dirk Dantz · Königslutter am Elm, DE
• Andreas Huber · Holzgerlingen, DE
• Ulrich Lambert · Emmerting, DE
• Reinhold Wahlich · Burghausen, DE

Key dates

• Filing date: May 25, 2004
• Grant date: Oct 17, 2006
• Expiry date: May 25, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76254
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An SOI wafer, includes a substrate made from silicon, an electrically insulating layer with a thermal conductivity of at least 1.6 W/(Km) and a single-crystal silicon layer with a thickness of from 10 nm to 10 μm, a standard deviation of at most 5% from the mean layer thickness and a density of at most 0.5 HF defects/cm2.A process is for producing an SOI wafer of this type, in which a substrate wafer made from silicon is joined to a donor wafer via a layer of the electrically insulating material which has previously been applied. The donor wafer bears a donor layer of single-crystal silicon, with a concentration of vacancies of at most 1012/cm3 and of vacancy agglomerates of at most 105/cm3. After the wafers have been joined, the thickness of the donor wafer is reduced in such a manner that the single-crystal silicon layer having these properties is formed from the donor layer, this single-crystal silicon layer being joined to the substrate wafer via the layer of electrically insulating material.