Methods of forming a multilayer stack alloy for work function engineering
US7122870B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2004 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Sep 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.