Semiconductor package structure
US7122893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2004 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Sep 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes a semiconductor component, a substrate, solder bumps, underfill, a buffer means, and solder balls. The substrate is under the semiconductor component. A joint area is formed between the first surface of the semiconductor and the upper surface of the substrate. Several solder bumps are disposed in the joint area, for electrically connecting the semiconductor component and the substrate. The underfill is filled in the joint area, for coating the solder bumps and tightly jointing the semiconductor component and the substrate. The buffer means is situated in the jointing area, for buffering the underfill to be confined in the joint area. Several solder balls are disposed on the lower surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.