Soft core control of dedicated memory interface hardware in a programmable logic device
US7123051B1 · kind B1 · utility
34Cited by
53References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2004 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Jun 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a soft core logic circuit implemented in a PLD that estimates an appropriate phase delay and applies the phase shift to a read strobe signal to align its rising and falling edges at the center of a data sampling window associated with a group of read data signals. The soft core logic circuit dynamically determines an appropriate phase-shift value for the read strobe signal and adjusts the phase-shift to accommodate the environmental changes. The soft core logic circuit also introduces into the PLD various intermediate signals from a phase-shift estimator and a programmable phase delay chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.