Brian Johnson
176Patents
27h-index
136Co-inventors
93Inventor score
Filing activity: Dec 2, 1985 → Aug 9, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5761854A | Collapsible portable containerized shelter | Fixed Constructions | 210 | Expired |
| US6697926B2 | Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device | Physics | 164 | Expired |
| US6434081B1 | Calibration technique for memory devices | Physics | 161 | Expired |
| US10732582B2 | Technologies for managing sensor malfunctions | Electricity | 106 | Active |
| USD706864S1 | Point of sale terminal | General | 98 | Active |
| USD707288S1 | Point of sale terminal | General | 97 | Active |
| US6801989B2 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same | Physics | 93 | Expired |
| US4761053A | Communications transmission media | Emerging Cross-Sectional Technologies | 85 | Expired |
| US4723831A | Optical fiber communications cable | Physics | 85 | Expired |
| USD849832S1 | Point of sale terminal | General | 83 | Active |
| US4935287A | Stretchable laminate constructions | Emerging Cross-Sectional Technologies | 80 | Expired |
| US5957791A | Lacrosse stick head with upper string holes and method for stringing same | Human Necessities | 70 | Expired |
| USD348654S | Hand held terminal with input keyboard and LCD display touch screen | General | 65 | Expired |
| US6462577B1 | Configurable memory structures in a programmable logic device | Electricity | 61 | Expired |
| US6889357B1 | Timing calibration pattern for SLDRAM | Electricity | 58 | Expired |
| US6687185B1 | Method and apparatus for setting and compensating read latency in a high speed DRAM | Physics | 55 | Expired |
| US6606041B1 | Predictive timing calibration for memory devices | Physics | 53 | Expired |
| US6836166B2 | Method and system for delay control in synchronization circuits | Electricity | 51 | Expired |
| US6658523B2 | System latency levelization for read data | Physics | 48 | Expired |
| US7051982B1 | Fairing arrangements for aircraft | Performing Operations; Transporting | 45 | Expired |
| US6807613B1 | Synchronized write data on a high speed memory bus | Physics | 37 | Expired |
| US6934199B2 | Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency | Physics | 37 | Expired |
| US7058799B2 | Apparatus and method for clock domain crossing with integrated decode | Physics | 36 | Expired |
| US7123051B1 | Soft core control of dedicated memory interface hardware in a programmable logic device | Physics | 34 | Expired |
| US6930955B2 | Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM | Physics | 33 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.