Flip-flop circuit having low power data retention
US7123068B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2005 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Jun 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop (10) has a normal mode and a low power mode to save power. The flip-flop (10) has a master latch (14) and a slave latch (20). The slave latch (20) is used to retain the condition of the flip-flop (10) during the low power mode, where power is withdrawn from the master latch (14) but maintained on the slave latch (20). The slave latch (20) may use transistors with lower leakage characteristics than the transistors that make up the master latch (14). These lower leakage characteristics may be achieved by a higher threshold voltage and/or a thicker gate dielectric. Operating speed of the flip-flop (10) is maintained by implementing the slave latch (20) so that no logic gate or switching transistor is in the critical timing path. Instead, the slave latch (20) has an input/output terminal to tap into the signal path between the master latch and an output circuit (22).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.