Power factor correction circuit and method of varying switching frequency
US7123494B2 · kind B2 · utility
22Cited by
10References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 6, 2003 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Dec 18, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power factor correction (PFC) circuit (10) includes a pulse width modulator (31) operating in response to a clock signal (CLK) for switching a coil current (ICOIL) over a charging period (TCHG) to correct a power factor at a node (32). The coil current discharges over a discharging period (TDSCHG) to develop an output voltage (VOUT) at an output (30). An oscillator (35) generates the clock signal to have a clock period (TCLK) longer than the sum of the charging and discharging periods, thereby operating in a discontinuous mode, and has an input (39) for sensing the input signal to modify the clock period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.