1P1N 2T gain cell
US7123500B2 · kind B2 · utility
27Cited by
69References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2003 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Dec 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.