Low latency multi-level communication interface
US7124221B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2000 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Jan 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0298
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM sigsnals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.