Carl W. Werner
83Patents
18h-index
45Co-inventors
84Inventor score
Filing activity: Jun 2, 1999 → May 10, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8199859B2 | Integrating receiver with precharge circuitry | Electricity | 139 | Active |
| US6772351B1 | Method and apparatus for calibrating a multi-level current mode driver | Electricity | 99 | Expired |
| US6370075B1 | Charge pump circuit adjustable in response to an external voltage source | Physics | 98 | Expired |
| US8498344B2 | Frequency responsive bus coding | Electricity | 88 | Active |
| US6184726A | Adjustable level shifter circuits for analog or multilevel memories | Physics | 86 | Expired |
| US7308058B2 | Transparent multi-mode PAM interface | Electricity | 80 | Expired |
| US6760262B2 | Charge pump circuit adjustable in response to an external voltage source | Physics | 79 | Expired |
| US7456778B2 | Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals | Electricity | 77 | Active |
| US7715471B2 | Signaling system with selectively-inhibited adaptive equalization | Electricity | 73 | Active |
| US6556465B2 | Adjustable circuits for analog or multi-level memory | Physics | 67 | Expired |
| US9165615B2 | Coded differential intersymbol interference reduction | Physics | 65 | Active |
| US7124221B1 | Low latency multi-level communication interface | Electricity | 56 | Expired |
| US7093145B2 | Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals | Electricity | 48 | Expired |
| US6208542A | Techniques for storing digital data in an analog or multilevel memory | Physics | 42 | Expired |
| US7308044B2 | Technique for receiving differential multi-PAM signals | Electricity | 28 | Expired |
| US7072415B2 | Method and apparatus for generating multi-level reference voltage in systems using equalization or crosstalk cancellation | Electricity | 27 | Expired |
| US6185119A | Analog memory IC with fully differential signal path | Physics | 24 | Expired |
| US7161513B2 | Apparatus and method for improving resolution of a current mode driver | Electricity | 23 | Expired |
| US7368961B2 | Clock distribution network supporting low-power mode | Physics | 18 | Expired |
| US8320494B2 | Method and apparatus for generating reference voltage to adjust for attenuation | Electricity | 16 | Active |
| US8331512B2 | Phase control block for managing multiple clock domains in systems with frequency offsets | Electricity | 16 | Active |
| US7626442B2 | Low latency multi-level communication interface | Electricity | 14 | Active |
| US7162672B2 | Multilevel signal interface testing with binary test apparatus by emulation of multilevel signals | Physics | 14 | Expired |
| US7764095B2 | Clock distribution network supporting low-power mode | Physics | 12 | Active |
| US7554844B2 | Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency | Physics | 11 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.