Virtual to physical memory address mapping within a system having a secure domain and a non-secure domain
US7124274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2003 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Aug 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/481
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for processing data, the apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including at least one secure mode being a mode in the secure domain; and at least one non-secure mode being a mode in the non-secure domain. When the processor is executing a program in a secure mode, the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor further includes a non-secure translation table base address register and a secure translation table base address register operable in the non-secure and secure domain, respectively, to indicate a region of memory storing either non-secure or secure domain memory mapping data defining how virtual addresses are translated to physical addresses within either the non-secure or secure domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.