Dummy fill for integrated circuits
US7124386B2 · kind B2 · utility
290Cited by
49References
84Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2002 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Mar 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/522
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.