Power MOSFET and methods of making same
US7126197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2004 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Jun 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a power MOSFET having a substrate of a first conductivity type and a body region of a second conductivity type. The method includes the steps of forming a gate region of a pre-determined pattern and with a plurality of gate elements partially covering the substrate. The gate element has a stepped cross-sectional profile with a thicker portion and a thinner portion. The thicker portion is adapted to substantially prevent passage of impurities therethrough into the substrate during the impurities implantation step. The thinner portion is adapted to allow partial passage of impurities therethrough during the impurities implantation step. Impurities are implanted into the substrate from the gate region side of the substrate to form a body region of the second conductivity type. After the impurities implantation step, a step-profiled body region, having a shallow body region and a deep body region, is formed in the substrate with impurities also present underneath pre-determined regions of the gate elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.